1. Field of the Invention
This invention relates generally to data processing system architectures, and more specifically to a programmable I/O bus adapter for coupling the I/O bus of a first data processor to the I/O bus of a second data processor so that data can be transferred back and forth between the two processors. The invention is adapted for use in circumstances where the two data processors are constructed in accordance with two substantially different computer architectures.
2. Description of the Prior Art
As the personal computer gains acceptance in the business world and in the scientific community, the need for connectivity between data processing systems has increased. However, currently existing data processing systems are organized according to one of a plurality of computer architectures. These computer architectures are often mutually incompatible, and a direct connection between two such incompatible systems will not yield meaningful results. Accordingly, various prior-art systems have been developed for the purpose of providing an interface between two data processors having incompatible architectures.
One commonly-utilized technique for providing an interface between two data processors employs a buffer storage mechanism for buffering the flow of data from one processor to another. The buffer storage mechanism may provide for bidirectional data flow. If it is desired to move a block of data from one processor to another, the block is transferred from a first processor to a buffer storage mechanism. Next, the block of data is read from the buffer storage mechanism and into the second data processor. Note that the two aforementioned transfers of data cannot take place simultaneously because all of the arriving data must be present in the buffer storage mechanism before the buffer can be read. These prior-art buffering techniques are often referred to as "store and forward" methods and/or "mailbox" methods.
Another prior art system provides an apparatus for transferring data between a master computer system having a first architecture and a slave element having a second architecture. Such a system is disclosed in U.S. Pat. No. 5,043,877, issued to Berger et al. on Aug. 27, 1991, and entitled, "Architecture Converter for Slave Elements", hereinafter referred to as Berger. The apparatus includes conversion circuitry for converting signals corresponding to the first architecture to signals corresponding to the second architecture. The conversion circuitry also has the capability of converting signals corresponding to the second architecture to signals corresponding to the first architecture.
The Berger system is designed for use with a master computer system using Extended Industry Standard Architecture (EISA) buses. The slave element uses an architecture known as Micro Channel, available from the International Business Machines (IBM) Corporation of Armonk, NY. Micro Channel is a trademark of the IBM Corp. Micro Channel computers provide a 32-bit data transfer format which is not directly compatible with EISA-type bus architecures.
While the EISA/Micro Channel conversion system is generally satisfactory, the device is designed to operate in the context of EISA and Micro Channel architectures. Furthermore, the system is adapted for use in circumstances where it is desired to employ a master element of a first architecture and a slave element of a second architecture. The master/slave system topology may not provide for optimum operational efficiency in the context of architectural combinations other than EISA/Micro Channel.
Another prior art system provides an integrated circuit chip designed to facilitate the connection of peripheral devices to a Micro Channel type architecture bus system. This system is disclosed in U.S. Pat. No. 4,991,085, issued to Pleva et al. on Feb. 5, 1991, and entitled, "Personal Computer Bus Interface Chip With Multi-Function Address Relocation Pins". The integrated circuit provides a partitioned interface so that microchannel signals and the protocol signals common to all functions are contained on a single interface chip.
Micro Channel systems use coded cycle commands in contrast to the uncoded memory I/O signals used on other types of systems, such as the IBM AT system architecture which has evolved into the de facto standard for one widely-available class of personal computers. Many basic peripheral devices for personal computers require uncoded command signals. In order to connect these devices to a Micro Channel type bus, logic must be provided to decode the bus status signals to provide the commands used and recognized by the peripheral devices.
Although the integrated circuit chip provides a useful interface for the connection of simple peripheral devices to Micro Channel buses, the chip is not designed for system applications where it is desired to connect two fully-integrated data processing systems having completely different system architectures. Such an application is beyond the capabilities of this integrated circuit chip.
An example of another prior-art system which is designed for use with peripherals and a host computer is the apparatus disclosed in Estrada et al., U.S. Pat. No. 4,855,905, issued on Aug. 8, 1989 (hereinafter referred to as Estrada). The Estrada device is an I/O controller which includes a data processing element for executing a sequence of stored program instructions. The stored program instructions control the transfer of data between specific I/O devices and the host computer. However, for reasons similar to those discussed above in conjunction with the Pleva patent, the Estrada device is not well suited for circumstances where it is desired to connect two fully-integrated data processing systems employing different bus architectures.
One technique for interconnecting two different data processing systems is described in U.S. Pat. No. 4,709,328, issued to Anthony, Jr., et al., on Nov. 24, 1987, and entitled, "Composite Data Processing System Using Multiple Standalone Processing Systems", hereinafter referred to as Anthony. The Anthony system interconnects the data processing systems into a single composite system by using a shared, dual-port memory area in the address space of each individual data processing system. A virtual channel is used to generate interrupts so that each data processing system can control the other. Each data processing system has the capacity to execute standalone programs.
The Anthony device includes a channel bus coupled to a host processor. The channel bus is adapted for connection to a plurality of I/O hardware adapters for the purpose of transferring I/O data and commands between the host processor and a plurality of I/O devices controlled by I/O hardware adapters. A virtual channel adapter is connected to the channel bus. The virtual channel adapter receives channel activation signals from the host processor, and produces control signals in response to the channel activation signals.
The purpose of the Anthony device is to provide a technique for the connection of a relatively complex business-type host computer system to a basic personal computer auxiliary system. Such personal computer systems frequently utilize one of three relatively simple I/O bus structures commonly known as the PC, XT, and AT systems. In this manner, the personal computer can be used to perform multiple functions for the host computer. However, the Anthony system is not well adapted for use in conjunction with Micro Channel systems, which use a relatively complicated asynchronous bus configuration.
Micro Channel systems offer significant performance advantages, and are particularly well-suited for certain specific types of system applications, as compared with conventional PC, AT, and XT systems. It would be desirable to have a technique for interconnecting two different data processing systems which is adaptable to relatively complex architectures, such as, for example, the Micro Channel environment.
Presently-existing Micro Channel processing systems include a planar processor for executing instructions, together with a memory device. A microchannel communications link provides an interface between the planar processor and one or more communications ports which are, for example, SCSI buses and/or local area network ports. One or more Micro Channel I/O adapters may be used in conjunction with the microchannel communications link.
Existing techniques which are applicable to Micro Channel environments do not offer optimum efficiency and speed, because many tasks are delegated to the Micro Channel planar processors. These tasks include IBM System S/390 I/O channel and control unit emulation. The execution of these tasks by the planar processors significantly reduces Micro Channel system performance.
What is needed is an improved system for providing a processor-to-processor interface. The interface should enable faster data transfer rates between the two processors than is currently possible with existing system topologies. It is also desirable to provide an improved interface mechanism which enables multiple, concurrent, independent processor to processor operations. The interface should include facilities for emulating the channel and the control unit so that the planar processor of the Micro Channel can be utilized more efficiently.